The present invention relates to a nonvolatile semiconductor memory device.
A basic operational principle of a nonvolatile memory is that an electric charge is injected into or discharged from a floating gate, and a logical “1” or a logical “0” is determined by a change in threshold value of a detection transistor or the like (JP-A-11-233654). The write method is divided into a method utilizing a hot carrier and a method utilizing an FN current. However, since either method uses the floating gate, the presence of a parasitic capacitor near the floating gate causes a problem. In many cases, the write characteristics are changed to a large extent due to the presence or absence of a small parasitic capacitor.
For example, when writing data by utilizing the capacitance ratio, a large capacitance ratio is necessary for applying a relatively high voltage to the floating gate. The layout area must be increased in order to increase the capacitance ratio, whereby the parasitic capacitance is increased. It is necessary to further increase the size of the capacitor so that the parasitic capacitor can be ignored. This results in a vicious circle.
Since most of the parasitic capacitors are formed by coupling with a substrate, it is necessary to take the parasitic capacitors into consideration when calculating the capacitance ratio. However, it is difficult to accurately calculate the parasitic capacitors included in a complicated three-dimensional shape. As a result, confirmation by trial manufacture is necessary so that a reduction in development cost is hindered.